I happened to know that there is a repository for OpenOCD for CH32V series MCUs.
https://github.com/kprasadvnsi/riscv-openocd-wch
From the following tweets, it looks that the source code in this repository was coming from MounRiver.
https://mobile.twitter.com/kprasadvnsi/status/1508643293176872962
Of course, we can flash CH32V series MCUs using tools that we can download from MounRiver’s site for free. But these tools are all only provided in binaries at this moment. I also could not find any clear instructions on how to build and use the tool in the above repository. I believe that having options to build important tools like a flash programming tool for an MCU – in this case, OpenOCD – is important.
I tried to build and test the OpenOCD in the above repository on my Ubuntu 20.04 installation to get an idea of what we can do with this code. Luckily I was able to build without a major issue and flash an actual CH32V307. So I decided to report my trial on this blog.
The following is the record of my trial on Ubuntu 20.04.
sudo apt install git make libtool texinfo libusb-1.0-0-dev libhidapi-dev libjaylink-dev<br>git clone https://github.com/kprasadvnsi/riscv-openocd-wch/<br>cd riscv-openocd-wch/<br>./bootstrap<br>./configure CFLAGS="-Wno-error" --enable-wlink<br>make
I saw many warnings during the build, but the above procedure gave me the OpenOCD binary under the src/ directory.
To be able to access a WCH-Link (WCH’s USB flash programmer for CH32V series MCUs) from Ubuntu, I went to MounRiver’s download page and downloaded MRS_Toolchain_Linux_x64_V1.40.tar.xz in the “Linux” tab. Then I uncompressed the downloaded file, copied an udev rule file, and reloaded the newly added rule file.
cd ~/Downloads tar Jxvf MRS_Toolchain_Linux_x64_V1.40.tar.xz sudo cp ~/Downloads/MRS_Toolchain_Linux_x64_V1.40/beforeinstall/50-wch.rules /etc/udev/rules.d/ sudo udevadm control --reload-rules
I went back to the riscv-openocd-wch/src directory where I built the OpenOCD binary again. I copied the wch-riscv.cfg file to this directory from the MRS_Toolchain_Linux_x64_V1.40 directory.
cp ~/Downloads/MRS_Toolchain_Linux_x64_V1.40/OpenOCD/bin/wch-riscv.cfg .
I tested my OpenOCD binary with WCH’s CH32V307RCT6 evaluation board (CH32V307V-EVT-R1). Erasing, programming, and verifying operations were all worked.
Program
sudo ./openocd -f wch-riscv.cfg -c init -c halt -c "program CH32V307RCT6.hex" -c exit
Erase
sudo ./openocd -f wch-riscv.cfg -c init -c halt -c "flash erase_sector wch_riscv 0 last" -c exit
Verify
sudo ./openocd -f wch-riscv.cfg -c init -c halt -c "verify_image CH32V307RCT6.hex" -c exit
Reset
sudo ./openocd -f wch-riscv.cfg -c init -c halt -c wlink_reset_resume -c exit
NoteCH32V307RCT6.hex is the firmware file I used to test the programming and verifying operations for CH32V307RCT6.
[Added on 2022-05-03] I generated this hex file from MounRiver Studio’s project template for CH32V307RCT6. After booting up, this firmware will output the following message to the UART.
SystemClk:72000000 This is printf example